1. Field of the Invention
The present invention relates to a nonvolatile EPROM, EEPROM or FLASH-EEPROM memory with tunnel oxide protection.
Though applicable to all the above types of memory, the present invention is particularly advantageous in the case of flash-EEPROM memories to which special reference is made in the following description.
2. Discussion of the Related Art
Flash-EEPROM memories are Electrically Erasable Programmable Read Only Memories (EEPROMS), which combine the high density and low cost of EPROMs with the advantage of electrical erasability. They have recently become the most attractive of nonvolatile memories for their potential application in solid state disks for portable computers.
Though various flash memory concepts have been developed, most flash memories employ a very thin (8-12 nm) oxide layer through which each memory cell may be programmed and erased by Fowler-Nordheim tunneling, and which is therefore known as the "tunnel oxide."
The following description deals with the most commonly used flash-EEPROM cell structure, the double-Poly single-transistor cell, though the present invention applies to any cell structure employing tunnel oxide.
Double-poly single-transistor flash cells present a structure closely resembling that of standard EPROM cells, and comprise an NMOS transistor with a, polysilicon floating gate region capacitively coupled to a second polysilicon layer defining a control gate. The main difference between these two types of cell lies in the thickness of the oxide between the floating gate region and the substrate, which is much thinner in the case of flash cells.
For the sake of clarity, a description will now be given of a flash-EEPROM cell with reference to the cross section shown in FIG. 1.
Number 1 in FIG. 1 indicates a flash-EEPROM cell formed, in this case, in a P type substrate 2 housing N+ type source and drain regions 3 and 4 separated by a channel region 5 formed by the substrate itself. Over substrate 2, aligned with channel 5, there are provided a floating gate region 6, fully embedded in an oxide layer 8, and a control gate region 7. Floating gate region 6 is separated from the substrate by a thin oxide layer 8a; control gate region 7 is separated from floating gate region 6 by a oxide portion 8b and source region 3 presents a graded junction with the substrate, that is, is formed in two parts: a heavily doped (N+) part 3a facing the larger surface 10 of the substrate; and a deeper, lightly doped (N-) part 3b surrounding part 3a on the sides not facing surface 10.
The yield and reliability of flash memories are known to be closely related to the quality of the tunnel oxide, which not only depends on preoxidation cleaning and the oxidation process itself, but is also strongly affected by the post-oxidation process steps.
Of all the process steps, the most critical are those which expose the wafer to radiation damage, namely ion implantation, plasma etching, sputtering and plasma enhanced chemical vapor deposition.
Currently used flash-EEPROM memory processes present a large number of such steps following growth of the tunnel oxide.
The model generally accepted for explaining in-process radiation is the so-called "antenna effect" in which charges are trapped in conductive layers and may result in a critical increase in the potential of the layers.
To explain the phenomenon, it should be borne in mind that ion implantation and plasma processes involve the collision of charge particles (either electrons or ions) with the wafer surface, so that conductive polysilicon layers insulated from the silicon substrate may be charged by capturing the charge particles.
If the polysilicon layer is not patterned, it acts as an electrostatic shield. In fact, the charge is distributed evenly over the entire area of the wafer, thus generating a low electric field. This is also because, in the case of ion implantation, the beam is localized and the overall charge density is low. In addition, the metal grips holding the wafer may act as discharge lines f or at least partly removing the captured charge particles, so that little danger exists for the dielectric layer underlying the polysilicon.
If, on the other hand, the layer is patterned and comprises "islands", i.e., areas insulated conductively from the rest of the layer and separated from the substrate by a thin oxide layer, as in the case of gate regions, the layer is charged to a potential that depends on the collecting area and its capacity versus the substrate, i.e., the area of the thin oxide. If the ratio between the collecting area and the area of the thin oxide is unfavorable (high), the gate region may easily reach a potential higher than the breakdown voltage of the thin oxide, thus resulting in oxide breakdown--in turn, resulting in "zero time" device failure, i.e., before it is even used--or in oxide damage with the formation of traps in the oxide itself and which, in turn, results in "latent" device failure and impaired reliability.
The above model also applies to flash cells. In fact, in certain situations, the tunnel oxide may be damaged due to capacitive coupling of the control and floating gate regions, and the lower dielectric resistance of the tunnel oxide in relation to the dielectric layer separating the control and floating gates. The likelihood of this occurring is even greater, in view of the extensive collecting area defined by the polysilicon strips forming the control gates, and the small area of the tunnel oxide of each cell. Consequently, the tunnel oxide may be broken or damaged in the event the control gate region is charged to a potential greater than the breakdown voltage of the tunnel oxide divided by the coupling factor of the control gate.
At present, the only way of minimizing-the "antenna effect," as described above, is to modify the process by exposing the wafer, in the case of high-current implantation, to an electron "shower" to compensate for the positive charge produced by the ion beam, or by optimizing the plasma etching process to reduce radiation damage. Such solutions, however, complicate the process and are difficult to control.
It is an object of the present invention to prevent post-oxidation, in-process radiation damage of the tunnel oxide, while at the same time eliminating the disadvantages of known solutions.